The disclosure relates generally to systems that employ virtual memory systems and more particularly to systems that employ virtual to physical memory address translation management.
Many computer operating systems such as those used in smart phones, tablet devices, laptops, servers, digital televisions and other devices employ a virtual addressing system wherein physical addresses of memory are mapped to virtual addresses being used by processes executing in the computer operating system. In such systems, every process is given the impression that it is working with large, contiguous sections of memory. In realty, each processes memory may be dispersed across different areas of physical memory or may have been paged out to backup storage such as a hard drive. Systems typically employ, for example, three levels of memory, cache memory, main memory such as DRAM and backup storage typically in the form of a hard drive, or other suitable persistent memory. When a process wishes to obtain information from memory, the information may be stored in the main memory. However, if it is not and must be obtained from the hard drive (which may be flash memory based), it can take as long as 20 milliseconds to respond to a request to obtain a 2 megabyte page to the hard drive.
This occurs, for example, when the CPU (central processing unit) uses the operating system to determine a page fault which means that the memory page being sought by the process is not in the main memory so the CPU needs to obtain the information from the hard drive source. If the page is not in the main memory, the page fault must be corrected by obtaining the page from the hard drive. For example, a driver executing on the CPU may pause an application so that a page may be obtained from the hard drive and placed in main memory. A page table is updated and the application is restarted. A problem can arise during context switches to load virtual address page fault routines since the CPU must carry out an access to a physical disk or persistent storage system in which the access time associated with locating the data and its transmission time once it is located may be significant (e.g., 20 milliseconds or more). Virtual memory paging structures are based on a complex relationship between three factors: (1) the likelihood that data locality will use more data, contiguous to the target data, (2) the amount of time it takes to access the target data, plus as much more as is deemed effective, and (3) the time it takes to transfer the target data to memory. The assumption that the hard drive access will take a very long time and hence the amount of data collected per access can be relatively large because access latency dominates transfer latency (currently, data transmission times for the hard drive are five or more orders of magnitude less than the data access times). Conversely, smaller page sizes allow more pages to be placed in the same memory footprint, increasing the relative effectiveness of the memory (fewer unneeded bytes of storage have been fetched in association with needed storage bytes. Conversely, smaller pages require more page mapping overhead (larger/deeper page tables) which also decreases a translation look aside buffer's effectiveness.
The CPU's memory management unit stores a cache of recently used mappings from the operating system's page table referred to as a translation look aside buffer (TLB). A page table is the data structure used by a virtual memory system to store the mapping between virtual addresses and physical addresses. When a virtual address needs to be translated into a physical address, the TLB is searched first. If a match is found, the physical address is returned and memory access can continue. However, if there is no match, the hardware (or sometimes a software driver or handler) in the CPU will look-up the address mapping in the page table to see whether a mapping exists by performing a page table walk. If a mapping exists in the page table, the mapping is written back to the TLB and the faulting instructions are restarted. The subsequent translation will find a TLB hit and the memory access will continue.
The page table holds the mapping between a virtual address of a page in the address of a physical block of memory. There is also additional information about the page such as a present bit (indicating whether the associated data is in memory or is still on the disk), a dirty bit (indicating that the associated data has been modified and will need to be copied back onto disk before the page can be re-allocated), and, if present, the address of the associated page in memory. Hard drive memory also referred to as secondary storage can be used to augment the physical memory and pages can be swapped in and out between the main memory and the hard drive. The present bit can indicate what pages are currently present in the main memory or those that are on the hard drive and communicate how to treat these different pages such as whether to load a page from the hard drive and swap another page into main memory out. These are well known operations.
However, there are page faults if the page table lookup targets a page that is not resident in the main memory. This could occur, for example, if the page had been swapped out of main memory to make room for another page or if the page is swapped to secondary backup store such as a hard drive. When this happens, the page needs to be taken from the secondary backup store (e.g., hard drive) and put back into the main memory. When physical memory is full, a page in physical memory needs to be swapped out to make room for the requested page. The page table needs to be updated to mark that the page that were previously in the physical memory is no longer there and to mark that the page that was on the hard disk is now on the physical or main memory. The TLB also needs to be updated, including removal of the swapped out page from it and the instruction is restarted.
The current paging scheme is optimized for memory architectures that have very high disk access latencies relative to memory access latencies. The optimizations will not be realized/effective if there is a fundamental change in the relationship between primary storage (memory) and secondary storage (disk) latencies. New memory architectures will require new management structures to realize their full potential.